I mean, the chipsets work all the same for all three current K8 sockets. Not all of them could work at the 1Ghz HT speeds, but they would still work.
And oh yeah, AMD has launched on VIA before. And don't forget ATI, SIS, ULI, and *gasp* AMD itself have been known to release a product every now and then.
They have done so in the past, but if you haven't noticed we're not getting a lot of news about VIA-based motherboards these days. We may see M2 chipsets and boards as early as June, but I have a feeling that any delays are likely more a factor of getting the CPU and memory controller to work properly. Supporting a new RAM type isn't really a simple change, especially in a chip that's running at 2.0+ GHz. Better to launch a month or even three late then to launch an unstable product.
Well, the real question is whether the M2 chips will use the same HT version as now or some newer version?
Considering how K8 strugles for HT bandwith IMHO new K8 cpu's will be elecrically supported by all current and past chipsets(maybe except nF3 150).
The only thing except a bit different wiring cased by DDR2 slots will be requirement for 266 clock generator since only other frequency to change is DDR->DDR2.
HyperTransport is actually used for core-to-core as well as socket-to-socket communications. HT also is used as the connection to the Northbridge (or multiple chipsets in the case of some Opteron boards). Once you understand that, you can see that even 1000 MHz HT is rarely a bottleneck. For that matter, the switch from 800 MHz HT to 1000 MHz HT has very little impact on most applications. (The problem with nForce3 150 was that it was 600 MHz and 8-bits - upstream - as opposed to 800 MHz and 16-bits. That much of a difference will be more noticeable.)
Memory bandwidth and performance can be a limiting factor, but memory communication doesn't go over HT. If it did, perhaps we could have CPU sockets with 500 pins instead of 939. The extra 185 pins of 939 is almost entirely for the second memory channel. 128 pins are definitely required, but I'm not sure how many of the remainder link up to memory. Anyway, DDR2 is a memory controller change and can be done independently of HT changes.
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8 Comments
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Ecmaster76 - Tuesday, November 1, 2005 - link
Isn't Hypertransport still Hypertransport?I mean, the chipsets work all the same for all three current K8 sockets. Not all of them could work at the 1Ghz HT speeds, but they would still work.
And oh yeah, AMD has launched on VIA before. And don't forget ATI, SIS, ULI, and *gasp* AMD itself have been known to release a product every now and then.
johnsonx - Wednesday, November 2, 2005 - link
I thought Socket M2 is also bringing HyperTransport 2.0, which is what actually requires a new chipset.As always, I could be wrong.
JarredWalton - Wednesday, November 2, 2005 - link
They have done so in the past, but if you haven't noticed we're not getting a lot of news about VIA-based motherboards these days. We may see M2 chipsets and boards as early as June, but I have a feeling that any delays are likely more a factor of getting the CPU and memory controller to work properly. Supporting a new RAM type isn't really a simple change, especially in a chip that's running at 2.0+ GHz. Better to launch a month or even three late then to launch an unstable product.mino - Wednesday, November 2, 2005 - link
Well, the real question is whether the M2 chips will use the same HT version as now or some newer version?Considering how K8 strugles for HT bandwith IMHO new K8 cpu's will be elecrically supported by all current and past chipsets(maybe except nF3 150).
The only thing except a bit different wiring cased by DDR2 slots will be requirement for 266 clock generator since only other frequency to change is DDR->DDR2.
mino
JarredWalton - Wednesday, November 2, 2005 - link
HyperTransport is actually used for core-to-core as well as socket-to-socket communications. HT also is used as the connection to the Northbridge (or multiple chipsets in the case of some Opteron boards). Once you understand that, you can see that even 1000 MHz HT is rarely a bottleneck. For that matter, the switch from 800 MHz HT to 1000 MHz HT has very little impact on most applications. (The problem with nForce3 150 was that it was 600 MHz and 8-bits - upstream - as opposed to 800 MHz and 16-bits. That much of a difference will be more noticeable.)Memory bandwidth and performance can be a limiting factor, but memory communication doesn't go over HT. If it did, perhaps we could have CPU sockets with 500 pins instead of 939. The extra 185 pins of 939 is almost entirely for the second memory channel. 128 pins are definitely required, but I'm not sure how many of the remainder link up to memory. Anyway, DDR2 is a memory controller change and can be done independently of HT changes.
KristopherKubicki - Wednesday, November 2, 2005 - link
The few manufacturers adopting K8T900 say that there are so many bugs they might drop it in favor of a ULi or ATI chip.Kristopher
JarredWalton - Wednesday, November 2, 2005 - link
Ouch. LOL. Maybe they can get Sony to make a chipset as well?bob661 - Wednesday, November 2, 2005 - link
Ouch is right. Wow!